As semiconductor devices have become more highly integrated, nano-technology approaches have been developed for manufacturing semiconductor devices.
However, a lithography tool or material are insufficient for mass production and, thus, the size of the diameter of the wafer is enlarged. Also, the purchase cost of the tool and the process cost are excessively increased.
U.S. Pat. No. 5,142,350 describes a method of forming a gate after depositing an epitaxially grown silicon layer and a crystalline boron nitride layer on a substrate.
However, such conventional methods cause structural problems and result in high manufacturing cost for the semiconductor device.
In the accompanying drawings, like reference numerals appearing in the drawings represent like parts.